1. Technical Field
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a buffer control circuit of a semiconductor memory apparatus.
2. Related Art
In a semiconductor memory apparatus, a write command is inputted in a write operation, and data (i.e., see FIG. 1C, DQ) is inputted to a buffer in synchronization with the write command. The buffer is not always turned on but is on/off controlled to reduce current consumption. The on/off control of the buffer is implemented by a buffer control signal.
In detail, a conventional buffer control signal will be described below with reference to FIGS. 1A, 1B and 1C.
FIG. 1A is a delay circuit of a conventional buffer control circuit, and FIG. 1B is a decoder of the conventional buffer control circuit. FIG. 1C is a timing diagram of a buffer control signal in the conventional buffer control circuit.
FIG. 1A shows a delay circuit of a conventional buffer control circuit, which includes a plurality of multiplexers and a plurality of flip-flops (i.e., F/F). The flip-flops F/F may receive a clock signal clk and a multiplexer may be coupled to a ground voltage Vss as shown in FIG. 1A. If a command cmd is inputted, the command cmd is delayed under the control of command latency signals cwl<7:10>, and first to fourteenth delayed signals L<1:14> are to generated.
The command cmd may be a write command. The time from after the write command is inputted to a semiconductor memory apparatus to until an operation is actually performed according to the write command is referred to as a CAS write latency (cwl). The CAS write latency (cwl) is prescribed in a specification to have a limited value according to an operation frequency.
FIG. 1B illustrates a decoder of the conventional buffer control circuit, which includes a plurality of logic circuits. The decoder receives the fifth to fourteenth delayed signals L<5:14> and generates a buffer control signal endinds.
Referring to FIG. 1B, the decoder receives the fifth to fourteenth delayed signals L<5:14> which are sequentially generated by the delay circuit, and generates the buffer control signal endinds.
Accordingly, the buffer control signal endinds is generated from when the fifth delayed signal L5 is enabled and is retained until the fourteenth delayed signal L14 is disabled.
The timing of the buffer control signal endinds will be described with reference to FIGS. 1A, 1B, and 1C.
First, the case where a CAS (i.e., column address strobe) write latency value is 9 will be described.
In FIG. 1A, the delay circuit sequentially delays the command cmd (i.e., see FIG. 1C, WT write command) according to a control signal cwl9.
In FIG. 1B, the decoder receives the fifth to fourteenth delayed signals L<5:14> among the commands cmd delayed according to the control of the control signal cwl9, and generates the buffer control signal endinds.
In detail, comparing delay amounts in the delay circuit of FIG. 1A, the fifth delayed signal L5 is generated when the command cmd controlled by the control signal cwl9 is delayed by 4 cycles (4*tCK), and the tenth delayed signal L10 is generated when the command cmd controlled by the control signal cwl9 is delayed by 9 cycles (9*tCK).
The decoder of FIG. 1B receives the fifth delayed signal L5 and generates the buffer control signal endinds. Accordingly, when 4 cycles (4*tCK) elapse after the command cmd is inputted, the buffer control signal endinds is generated.
The control signal cwl9 is a signal which actually executes a command when 9 cycles (9*tCK) elapse after the command cmd is inputted. In the delay circuit of FIG. 1A, the tenth delayed signal L10 is generated when 9 cycles (9*tCK) elapse after the command cmd is inputted.
Accordingly, a command is actually executed after 5 cycles (5*tCK) from when the buffer control signal endinds is enabled (see FIG. 1C, cwl=9).
Next, the case where a CAS write latency value is 7 will be described.
In FIG. 1A, the delay circuit sequentially delays the command cmd (i.e., see FIG. 1C, WT write command) according to a control signal cwl7.
In FIG. 1B, the decoder receives the fifth to fourteenth delayed signals L<5:14> among the commands cmd delayed according to the control of the control signal cwl7, and generates the buffer control signal endinds.
In detail, comparing delay amounts in the delay circuit of FIG. 1A, the fifth delayed signal L5 is generated when the command cmd controlled by the control signal cwl7 is delayed by 2 cycles (2*tCK), and the tenth delayed signal L10 is generated when the command cmd controlled by the control signal cwl7 is delayed by 7 cycles (7*tCK).
The decoder of FIG. 1B receives the fifth delayed signal L5 and generates the buffer control signal endinds. Accordingly, when 2 cycles (2*tCK) elapse after the command cmd is inputted, the buffer control signal endinds is generated.
The control signal cwl7 is a signal which actually executes a command when 7 cycles (7*tCK) elapse after the command cmd is inputted. In the delay circuit of FIG. 1A, the tenth delayed signal L10 is generated when 7 cycles (7*tCK) elapse after the command cmd is inputted.
Accordingly, a command is actually executed after 5 cycles (5*tCK) from when the buffer control signal endinds is enabled (see FIG. 1C, cwl=7).
In this way, in the conventional art, since the pulse width of the buffer control signal endinds is fixed, a problem is caused in that unnecessary current consumption is caused.